1. Field of the Invention
The present invention relates to a combined phase-locked loop (PLL) and amplitude-locked loop (ALL) module for switching FM signals received from a co-channel. More particularly, the present invention relates to the combined phase-locked loop and amplitude-locked loop module implemented by using field programmable gate arrays (FPGAs).
2. Description of the Related Art
A phase-locked loop used in telecommunications, computer and consumer devices is well known to a person skilled in the art, and has been described in many U.S. patents. For example, the related U.S. patents include: U.S. Pat. No. 7,271,664, entitled “phase locked loop circuit;” U.S. Pat. No. 7,253,692, entitled “phase locked loop;” U.S. Pat. No. 7,206,369, entitled “programmable feedback delay phase-locked loop for high-speed input/output timing budget management and method of operation thereof;” U.S. Pat. No. 7,174,144, “calibration of a phase locked loop;” U.S. Pat. No. 7,170,965, entitled “low noise divider module for use in a phase locked loop and other applications;” U.S. Pat. No. 7,148,758, entitled “integrated circuit with digitally controlled phase-locked loop;” U.S. Pat. No. 7,095,992, entitled “phase locked loop calibration;” U.S. Pat. No. 7,082,295, entitled “on-chip loop filter for use in a phase locked loop and other applications;” U.S. Pat. No. 7,042,972, entitled “compact, low-power low-jitter digital phase-locked loop;” U.S. Pat. No. 7,002,419, entitled “metal programmable phase-locked loop;” U.S. Pat. No. 6,998,922, entitled “phase locked loop modulator calibration techniques;” U.S. Pat. No. 6,812,688, entitled “signal acquisition method and apparatus using integrated phase locked loop;” U.S. Pat. No. 6,801,092, entitled “phase locked loop that avoids false locking;” U.S. Pat. No. 6,771,715, entitled “demodulator using cordic rotator-based digital phase locked loop for carrier frequency correction;” U.S. Pat. No. 6,710,635, entitled “frequency and phase locked loop;” U.S. Pat. No. 6,703,875, entitled “device for emulating phase-locked loop and method for same;” U.S. Pat. No. 6,680,644, entitled “digital interpolation window filter for phase-locked loop operation with randomly jittered reference clock;” U.S. Pat. No. 6,542,040, entitled “phase-locked loop employing programmable tapped-delay-line oscillator;” U.S. Pat. No. 6,469,553, entitled “phase-locked loop circuitry for programmable logic devices;” U.S. Pat. No. 6,437,650, entitled “phase-locked loop or delay-locked loop circuitry for programmable logic devices;” U.S. Pat. No. 6,356,158, entitled “phase-locked loop employing programmable tapped-delay-line oscillator;” U.S. Pat. No. 6,356,129, entitled “low jitter phase-locked loop with duty-cycle control;” U.S. Pat. No. 6,356,127, entitled “phase locked loop;” U.S. Pat. No. 6,271,729, entitled “phase-locked loop or delay-locked loop circuitry for programmable logic devices;” U.S. Pat. No. 6,218,876, entitled “phase-locked loop circuitry for programmable logic devices;” U.S. Pat. No. 6,177,844, entitled “phase-locked loop or delay-locked loop circuitry for programmable logic devices;” U.S. Pat. No. 6,133,769, entitled “phase locked loop with a lock detector;” and U.S. Pat. No. 5,999,025, entitled “phase-locked loop architecture for a programmable logic device.” Each of the above-mentioned U.S. patents is incorporated herein by reference for purposes including, but not limited to, indicating the background of the present invention and illustrating the state of the art.
An amplitude-locked loop also known in the art is constituted by a circuitry which embodies all the principles of the PLL but operates in the amplitude domain or real domain and not in the frequency or imaginary domain. For example, U.S. Pat. No. 5,341,106, issued to Pettigrew on Aug. 23, 1994, discloses a circuit using an amplitude-locked loop and a phase-locked loop to remove AM crosstalk from an FM signal, which is incorporated herein by reference for purposes including, but not limited to, indicating the background of the present invention and illustrating the state of the art.
With regard to the problematic aspects naturally occurring during the use of the PLL or ALL circuit, it cannot provide a function of exchanging or switching FM signals received from a co-channel while removing the effect of co-channel interference (CCI) and recovering the messages from carriers. Hence, there is a need for improving the function of the PLL or ALL circuit for providing the function of exchanging or switching FM signals received from a co-channel.
As is described in greater detail below, the present invention intends to provide a combined PLL and ALL module for switching FM signals received from a co-channel. The combined PLL and ALL module is preferably implemented by using FPGAs. The combined PLL and ALL module is controlled to process FM signals by adjusting the ratio of second amplitude to first amplitude to closely approach a predetermined value. Hence, FM signals are separated and switched by the combined PLL and ALL module in such a way as to mitigate and overcome the above problem.